Basic Pulse Circuits - Part 3: Metastability, Setting, or Resetting

In digital design, signal processing is crucial when dealing with asynchronous signals from sensors and level translators. In Part 1 of a three-part series, Wolfgang described how pulse circuits help digital circuits deal with pulse trains. In Part 2, he wrote about flip-flops, timing parameters and synchronization. In Part 3, he looks at how to mitigate metastability and ensure internal clock synchronization.

- Wolfgang Matthes

Many digital systems must process signals from outside with sensors and level translators. The signals are mostly pulse trains or bursts of pulses. Some pulses may be too narrow, some may be too wide, and other pulse trains may be affected by glitches. Designers need to learn about capturing pulses, detecting edges, filtering out or detecting glitches, and synchronizing the pulses with internal clocks. In the first part of this three-part article in Circuit Cellar Issue #413, we introduced the latches and flip-flops as the most basic components to address these fundamental design problems.

In Issue #414, I examined how to implement the flip-flop behavior like enabling and resetting, timing parameters, and synchronization. In Part 3, I will look further into the problem of metastability and related subtleties of setting or resetting.

These are minor but intricate problems that most textbooks do not adequately cover. Solving such complex problems requires some familiarity with the appropriate components and careful attention to the minute details involved in the process.

METASTABILITY IN PRACTICE