MORE-THAN-MOORE SOC: RISC-V, Chiplets, And Heterogeneous Integration

Ride the More-than-Moore wave! Established CPU and GPU giants are already on board, but it is the emerging startups leveraging RISC-V, chiplets, and heterogeneous integration that hold the key to a future of unparalleled Al-friendly SoC development

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More-than-Moore (MtM) is a concept and strategy in semiconductor design that extends beyond the traditional Moore's Law scaling of packing more transistors into a given silicon area (monolithic chips) to achieve performance gains. The MtM philosophy is fundamental as the physical and economic limits of traditional silicon scaling become apparent.

MtM aims to enable new applications by combining different technologies according to their functional needs rather than just focusing on making transistors smaller or faster. This strategy is increasingly seen as essential for the future of the semiconductor industry, enabling innovation in areas where silicon chips are running out of room to provide more performance gain.

The primary use of MtM is for system-on-a-chip (SoC) design and manufacturing, mainly because SoCs, sooner or later, will reach the reticle (photomask) limit. The reason is the theoretical EUV-based lithography reticle limit of 858mm², as the latest generation GPUs (following a monolithic approach) are already closer to 800mm².

It implies that there is little to no room to pack more transistors. Also, adopting the most advanced technology node to gain performance without increasing the area is slowly turning into a costly affair, with 3nm requiring more than $700 million to productise and 2nm needing more than $1 billion. Thus, there is a dire need to innovate SoC development.

MtM using RISC-V, chiplets, and heterogeneous integration

Out of all, the most promising combination of design and manufacturing approaches that will potentially speed up MtM adoption are RISC-V, chiplets, and heterogeneous integration.