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Handwritten Digit Recognition with FPGA-Powered CNNs

- Jichao Yang and Yiyang Zhao

Discover how FPGA-powered Convolutional Neural Networks (CNNs) revolutionize handwritten digit recognition, achieving impressive speeds and accuracy. This article delves into the innovative implementation on the DE1-SoC platform, showcasing the seamless integration of hardware and advanced machine-learning techniques.

In the fast-paced world of artificial intelligence, deep learning—a key branch of machine learning—has gained significant attention, especially in fields such as computer vision and image processing. Among the various deep learning models, Convolutional Neural Networks (CNNs) have become the go-to choice for image recognition and analysis.

Since Yann LeCun introduced the LeNet-5 model in 1998 for handwritten digit recognition, CNNs have been widely adopted. However, running these models in programming languages such as C or Python can be slow due to their sequential processing nature and memory bottlenecks. To address those issues, we implemented the CNN model for digit recognition on an FPGA with Verilog, a hardware description language that allows for hardware-level parallelism and efficient data management through on-board memory (SRAM). The implementation utilizes parallelization for both computations and memory accesses, enabling faster processing.

This article provides an overview of how we implemented a CNN model on the DE1-SoC, a hardware design platform that includes the Altera Cyclone V FPGA and dual-core Cortex-A9 embedded cores, utilizing hardware-level parallelism. It explains the CNN architecture, the DE1-SoC board we used, the communication between the FPGA and hard processor system (HPS), and outlines the digit recognition process.

TRADITIONAL APPROACH FOR HANDWRITTEN DIGIT RECOGNITION