Basic Pulse Circuits

In part one of a three-part series, Wolfgang wrote how basic pulse circuits help digital circuits, such as embedded boards with ARM processors, deal with pulse trains or bursts of pulses from the outside. In Part 2, he dives into enabling flip-flops, timing parameters, and synchronization, design tasks needed to capture, detect, and filter pulses.

- Wolfgang Matthes

Part 2: Flip-Flops, Timing Parameters and Synchronization

Many digital systems must process signals from outside from sensors and level translators. The signals are mostly pulse trains or bursts of pulses. Some pulses may be too narrow, some may be too wide, and other pulse trains may be affected by glitches. Designers need to learn about capturing pulses, detecting edges, filtering out or detecting glitches, and synchronizing the pulses with internal clocks. In the first part of this three-part article, we introduced the latches and flip-flops as the most basic components to address these fundamental design problems. This month, we examine how to enable and disable flipflops, timing parameters and synchronization. These are minor but intricate problems most textbooks do not cover. Solving such problems requires some familiarity with the appropriate components and some inclination to deal with the utmost details.

ENABLING AND DISABLING FLIP-FLOPS

An enabled flip-flop will react to an appropriate clock edge precisely as commanded by its input signals. A disabled flip-flop disregards the input signals. It keeps its state and does nothing else. Whether the flip-flop is enabled or disabled is controlled by a clock enable (CE) signal. We could think of implementing this function by simply turning the flip-flop’s clock off if the clock enable signal (CE) is inactive (