It cannot be a co-incidence. One after another, a slew of top technology majors in the mobility space have started putting their weight and lab-aprons behind artificial intelligence (AI)-backed processing. There is Samsung that has begun using AI for automating computer chip design. Reportedly, it is using AI features in new software from Synopsys, and heading close to commercial processor design with AI. It could be a core part of its Exynos chips, which are used in smartphones.
Running with the AI jersey on this track are Google and Nvidia too – as we have noticed in their research papers and AI-directed initiatives. Google has been exploring it for its next generation TPU Chip and possibly for architectural optimization. For instance, we saw in a paper how it is using AI to arrange the components on the Tensor chips – they are used to train and run AI programs in its data centers. NVIDIA is also trying to use it for floor-planning. Then there is Cadence Design Systems that is jumping in this pool with an AI-based optimization platform.
A big difference that AI brings in chip-design and semiconductor space for smartphones and communication is on its ability to redefine space aspects. AI can bring in the much-loved autonomous advantage for identifying optimal ways to arrange silicon components (layouts) on a chip. This can help in reduction of area as well as in arresting power consumption. Plus, with reinforcement learning, it can check out a number of alternatives for design and knock-out the ones that don’t fit design goals; this matters a lot when there can be a gazillion ways to just place the components on a chip. And the difference between a chosen path and a better path can be humongous in terms of power savings and chip-efficiency.
AI can help in chip-design on all salient levels, as experts have pointed out. From the Behavioural level where architects define the chip’s purpose to the Structural level where chip organization is spelt out, to the Geometry level where chip lay-out is defined – AI can address many constraints of erstwhile methods – and also the Moore’s Law. Machine learning can help tremendously in improving the work on clock-trees which is a chip engineer’s, and a designer’s, area of interest.
What better than AI to arrange billions of transistors across a chip and address the complexity of chipdesign! Algorithms can be trained well to handle many permutations and combinations of multiple components. Without AI, this process takes weeks and a lot of manual or computational time. From placing the components to wiring them, to using simulation for finding out efficacy of a given design to the use of reinforcement learning for multi-pronged chip-goals; AI can really change the way chips are baked. AI can help a lot in improving economies of scale which were not so hard to achieve in traditional chips. As we see chips being directed for newer and more radical applications – this factor is becoming quite a huge one. Smartphones, cloud and 5G are putting new imperatives and innovations in the chip design space.
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